ICS 2014

28th International Conference on Supercomputing

Conference Program

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Tuesday, June 10

Workshops

Registration opens at 8:00.

  Room A Room B Room C
8:30 - 10:30 W1: ROSS W2: Auto-Tuning W3: Power and Performance Efficiencies for HPC
  BREAK
11:00 - 13:00 W1: ROSS W2: Auto-Tuning W3: Power and Performance Efficiencies for HPC
  LUNCH
14:30 - 16:30 W1: ROSS W4: Extreme Scaling W5: Exploiting Different Levels of Parallelism for Exascale Computing
  BREAK
17:00 - 19:00 W1: ROSS W4: Extreme Scaling W5: Exploiting Different Levels of Parallelism for Exascale Computing

Wednesday, June 11

Wednesday - Friday, June 11-13: Main conference and tutorials

  Room A Room B
8:30 - 9:00 Welcome  
9:00 - 10:00 Keynote Thomas Lippert
HPC for the Human Brain Project
 
  BREAK
10:30 - 12:30 S1: Programming Models  
  LAWS: Locality-Aware Work-Stealing for Multi-socket Multi-core Architectures
Quan Chen, Minyi Guo and Haibing Guan
 
  Effective Automatic Computation Placement and Data allocation for Parallelization of Regular Programs
Chandan Reddy and Uday Bondhugula
 
  On the Conditions for Efficient Interoperability with Threads: An Experience with PGAS Languages Using Cray Communication Domains
Khaled Ibrahim and Katherine Yelick
 
  HOMR: A Hybrid Approach to Exploit Maximum Overlapping in MapReduce over High Performance Interconnects
Md Rahman, Xiaoyi Lu, Nusrat Islam and Dhabaleswar Panda
 
  LUNCH
14:00 - 16:00 S2: Memory Systems T1: Hybrid PGAS
  DTail: A Flexible Approach to DRAM Refresh Management
Zehan Cui, Sally A. McKee, Zhongbin Zha, Yungang Bao and Mingyu Chen
 
  Last-Level Cache Deduplication
Yingying Tian, Samira Khan, Daniel Jiménez and Gabriel Loh
 
  Block Value based Insertion Policy for High Performance Last-level Caches
Lingda Li, Junlin Lu and Xu Cheng
 
  Multi-Stage Coordinated Prefetching for Present-day Processors
Sanyam Mehta, Zhenman Fang, Antonia Zhai and Pen-Chung Yew
 
  BREAK
16:30 - 18:30 S3: Applications and Algorithms T1: Hybrid PGAS
  Evaluation of Methods to Integrate Analysis into a Large-Scale Shock Physics Code
Ron Oldfield, Kenneth Moreland, Nathan Fabian and David Rogers
 
  Input-adaptive Parallel Sparse Fast Fourier Transform for Stream Processing
Shuo Chen and Xiaoming Li
 
  Thread-cooperative, bit-parallel computation of Levenshtein distance on GPU
Alejandro Chacón, Santiago Marco-Sola, Antonio Espinosa, Paolo Ribeca and Juan Carlos Moure
 
  Load Balancing N-body Simulations with Highly Non-Uniform Density
Olga Pearce, Todd Gamblin, Bronis de Supinski, Tom Arsenlis and Nancy Amato
 
18:45 - 20:15 Guided Walking Tour

Thursday, June 12

  Room A Room B
8:30 - 9:30 Keynote Marc D. Hill
21st Century Computer Architecture
 
9:30 - 10:00 High-Performance Computing in Horizon 2020
Panagiotis Tsarchopoulos, EC
 
  BREAK
10:30 - 12:30 S4: MPI  
  MT-MPI: Multithreaded MPI for Many-core Environments
Min Si, Antonio Peña, Pavan Balaji, Masamichi Takagi and Yutaka Ishikawa
 
  Implementing a Classic: Zero-copy All-to-all Communication with MPI datatypes
Jesper Larsson Träff, Antoine Rougier and Sascha Hunold
 
  Value Influence Analysis for Message Passing Applications
Philip Roth and Jeremy Meredith
 
  Scalable Tracing of MPI Programs through Signature-Based Clustering Algorithms
Amir Bahmani and Frank Mueller
 
  LUNCH / Poster Session
14:00 - 16:00 S5: I/O and NVRAM  
  Revealing Applications' Access Pattern in Collective I/O for Cache Management
Yin Lu, Yong Chen, Rob Latham and Yu Zhuang
 
  Supporting Storage Configuration for I/O Intensive Workflows
Lauro Beltrao Costa, Samer Al-Kiswany, Hao Yang and Matei Ripeanu
 
  Understanding the Impact of Threshold Voltage on MLC Flash Memory Performance and Reliability
Wei Wang, Tao Xie and Deng Zhou
 
  DWC: Dynamic Write Consolidation for Phase Change Memory Systems
Fei Xia, Dejun Jiang, Jin Xiong, Mingyu Chen, Lixin Zhang and Ninghui Sun
 
  BREAK
16:30 - 18:30 S6: Modeling and Optimization  
  Palm: Easing the Burden of Analytical Performance Modeling
Nathan Tallent and Adolfy Hoisie
 
  An End-to-End Analysis of File System Features on Sparse Virtual Disks
Ruijin Zhou, Sankaran Sivathanu, Jinpyo Kim, Bing Tsai and Tao Li
 
  Improving Performance by Matching Imbalanced Workloads with Heterogeneous Platforms
Jie Shen, Henk Sips, Peng Zou, Yutong Lu and Ana Lucia Varbanescu
 
  Long-Term Resource Fairness: Towards Economic Fairness on Pay-as-you-use Computing Systems
Shanjiang Tang, Bu-Sung Lee, Bingsheng He and Haikun Liu
 
20:00 - 22:30 Conference Dinner

Friday, June 13

  Room A Room B
8:30 - 9:30 Keynote Marc Snir
The Future of Supercomputing
 
  BREAK
10:00 - 12:00 S7: Accelerators  
  Acceleration of Derivative Calculations with Application to Radial Basis Function – Finite-Differences on the Intel MIC Architecture
Gordon Erlebacher, Erik Saule, Natasha Flyer and Evan Bollig
 
  An Efficient Two-Dimensional Blocking Mechanism for Sparse Matrix-Vector Multiplication on GPUs
Arash Ashari, Naser Sedaghati, John Eisenlohr and P. Sadayappan
 
  A Programming System for Xeon Phis with Runtime SIMD Parallelization
Xin Huo, Bin Ren and Gagan Agrawal
 
  Unified On-chip Memory Allocation for SIMT Architecture
Ari Hayes and Eddy Z. Zhang
 
  LUNCH
13:30 - 15:00 S8: Interconnect and Microarchitecture  
  Galaxy: A High-Performance Energy-Efficient Multi-Chip Architecture Using Photonic Interconnects
Yigit Demir, Yan Pan, Sukwoo Song, Nikos Hardavellas, Gokhan Memik and John Kim
 
  A Performance Perspective on Energy Efficient HPC Links
Karthikeyan P. Saravanan, Paul M. Carpenter and Alex Ramírez
 
  Verifying Micro-architecture Simulators using Event Traces
Hui Meen Nyew, Nilufer Onder, Soner Onder and Zhenlin Wang
 
   
15:30 - 17:00 S9: Multi- and Many-core Systems  
  Scaling Up Matrix Computations on Shared-Memory Manycore Systems with 1000 CPU Cores
Fengguang Song and Jack Dongarra
 
  Collective Memory Transfers for Multi-Core Chips
George Michelogiannakis, Samuel Williams, Alexander Williams and John Shalf
 
  Scalable Analysis of Multicore Data Reuse and Sharing
Miquel Pericàs, Kenjiro Taura and Satoshi Matsuoka