The 4th Workshop on
UnConventional High Performance Computing 2011 (UCHPC 2011)
August 29th, Bordeaux, France

held in conjunction with
Euro-Par 2011, August 29th - September 2rd, 2011
Bordeaux, France

Invited Talks
Important Dates

Call for Papers
in txt format

Previous UCHPC
2010 @ EuroPar'10
2009 @ CF'09
2008 @ ICCSA'08

EuroPar 2011
Conference Home


The workshop program is now available! In addition to the talks for accepted papers, we are proud to present two invited speakers: Raymond Namyst will talk about the programming heterogenous systems, and Bertil Schmidt about GPU usage for bioinformatics.


Photo by Olivier Aumage
As the word "UnConventional" in the title suggests, the workshop focuses on hardware or platforms used for HPC, which were not intended for HPC in the first place. Reasons could be raw computing power, good performance per watt, or low cost in general. Thus, UCHPC tries to capture solutions for HPC which are unconventional today but perhaps conventional tomorrow. For example, the computing power of platforms for games recently raised rapidly. This motivated the use of GPUs for computing (GPGPU), or even building computational grids from game consoles. The recent trend of integrating GPUs on processor chips seem to be very beneficial for use of both parts for HPC. Other examples for "unconventional" hardware are embedded, low-power processors, upcoming many-core architectures, FPGAs or DSPs. Thus, interesting devices for research in unconventional HPC are not only standard server or desktop systems, but also relative cheap devices due to being mass market products, such as smartphones, netbooks, tablets and small NAS servers. For example, smartphones seem to become more performance hungry every day. Only imagination sets the limit for use of the mentioned devices for HPC.


The goal of the workshop is to present latest research in how hardware and software (yet) unconventional for HPC is or can be used to reach goals such as best performance per watt. UCHPC also covers according programming models, compiler techniques, and tools. Thus, suggested topics for papers include, but are not limited to the following:
  • Innovative use of hardware and software unconventional for HPC
  • HPC applications or visualizations in connection with HPC on GPUs (GPGPU), low power/embedded processors, FPGAs, Intel's new Knights Corner and SCC research processors, Tilera's tile-based many-core processors, IBM Cell BE, concepts for AMD Fusion, accelerators, visualization cards, etc.
  • Cluster/Grid solutions using unconventional hardware, e.g. clusters of game consoles, nodes using GPUs, Low Power/Embedded Processors, MPSoCs, new many-cores from Intel and/or ARM designs, Mac Minis/AppleTVs, FPGAs etc.
  • Heterogeneous computing on hybrid platforms
  • Performance and scalability studies in HPC using unconventional hardware
  • Reconfigurable Computing for HPC
  • Performance modeling, analysis and tools for HPC with unconventional hardware
  • New or adapted/extended (parallel) programming models for HPC with unconventional hardware

Invited Talks

We are proud to have two invited talks this year. For the time schedule, see the program section below.

Programming Heterogeneous, Accelerator-based Multicore Machines: a Runtime System's Perspective
Raymond Namyst


    Heterogeneous accelerator-based parallel machines, featuring manycore CPUs and with GPU accelerators provide an unprecedented amount of processing power per node. Dealing with such a large number of heterogeneous processing units -- providing a highly unbalanced computing power -- is one of the biggest challenge that developpers of HPC applications have to face. To Fully tap into the potential of these heterogeneous machines, pure offloading approaches, that consist in running an application on regular processors while offloading part of the code on accelerators, are not sufficient.
    In this talk, I will go through the major programming environments that were specifically designed to harness heterogeneous architectures, focusing on runtime systems. I will discuss some of the most critical issues programmers have to consider to achieve portability of performance, and I will show how advanced runtime techniques can speed up applications in the domain of dense linear algebra.
    Eventually, I will give some insights about the main challenges designers of programming environments will have to face in upcoming years.

Algorithms and Tools for Bioinformatics on GPUs
Bertil Schmidt


    The enormous growth of biological sequence data has caused bioinformatics to be rapidly moving towards a data-intensive, computational science. As a result, the computational power needed by bioinformatics applications is growing rapidly as well. The recent emergence of parallel accelerator technologies such as GPUs has made it possible to significantly reduce the execution times of many bioinformatics applications. In this talk I will present the design and implementation of scalable GPU algorithms based on the CUDA programming model in order to accelerate important bioinformatics applications. In particular, I will focus on algorithms and tools for next-generation sequencing (NGS) using error correction as an example. Detection and correction of sequencing errors is an important but time-consuming pre-processing step for de-novo genome assembly or read mapping. In this talk, I discuss the parallel algorithm design used for the CUDA-EC and DecGPU tools. I will also give an overview of other CUDA-enabled tools developed by my research group.


The workshop takes place on August, 29th. It is scheduled as half-day in the afternoon.

14:30 Welcome and Introduction by Workshop Organizers
Josef Weidendorfer, Jan-Philipp Weiss
  Session 1: Heterogeneous Systems
Chair: Jan-Philipp Weiss
14:40 Invited Talk 1
Programming Heterogeneous, Accelerator-based Multicore Machines: a Runtime System's Perspective
Raymond Namyst
15:20 PACUE: Efficient Heterogeneous Processor Allocations in PCs
Tetsuro Horikawa, Michio Honda, Jin Nakazawa, Kazunori Takashio, Hideyuki Tokuda
15:40 Workload Balancing on Heterogeneous Systems: A Case Study of Sparse Grid Interpolation
Alin Murarasu, Josef Weidendorfer and Arndt Bode
16:00 Coffee Break
  Session 2: Accelerator Usage for Applications
Chair: Josef Weidendorfer
16:30 Invited Talk 2
Algorithms and Tools for Bioinformatics on GPUs
Bertil Schmidt
17:00 Performance Evaluation of a Multi-GPU Enabled Finite Element Method for Computational Electromagnetics
Tristan Cabel, Joseph Charles and Stéphane Lanteri
  Session 3: Upcoming Architectures
Chair: Peter Zinterhof
17:20 Study of Hierarchical N-Body Methods for Network-on-Chip Architectures
Thomas Canhao Xu, Pasi Liljeberg and Hannu Tenhunen
17:40 Extending a Highly Parallel Data Mining Algorithm to the Intel Many Integrated Core Architecture
Alexander Heinecke, Michael Klemm, Dirk Pflüger, Arndt Bode, Hans-Joachim Bungartz
18:00 Workshop Closing

Paper Submission, Registration, and Publication

Workshop papers should not exceed eight single-spaced, single-column pages. As this is a workshop on a fast evolving topic, we encourage you to enhance your contribution with newest measurements even after the acceptance decision, but keep the total page limit in mind. Submission implies that at least one author will register for the workshops at Euro-Par 2011 and present the paper in the workshop session, if accepted.

Upload your submission to our submission server in PDF format. It must not be simultaneously submitted to the main conference or any other publication outlet.

For the workshop, we will prepare handouts with the revised papers. After a short check by the reviewers, these will be published after the conference in the workshop proceedings of Euro-Par 2011, part of the LNCS series of Springer.

Important Dates

June 22: Submission deadline (was June 12)
July 25: Notification of acceptance
August 22: Revised papers due
August 29/30: Conference with workshops
October 2: Final review comments
October 16: Camera ready papers for EuroPar Workshop Proceedings


International Program Committee

David A. Bader, Georgia Tech, US
Michael Bader, Universität Stuttgart, DE
Denis Barthou, Universite de Bordeaux, FR
Lars Bengtsson, Chalmers, SE
Karl Fürlinger, LMU, Munich, DE
Dominik Göddeke, TU Dortmund, DE
Georg Hager, University Erlangen-Nuremberg, DE
Anders Hast, University of Gävle, SE
Ben Juurlink, TU Berlin, DE
Rainer Keller, HLRS Stuttgart, DE
Gaurav Khanna, University of Massachusetts Dartmouth, US
Harald Köstler, University Erlangen-Nuremberg, DE
Dominique Lavenier, INRIA, FR
Manfred Mücke, University of Vienna, AT
Andy Nisbet, Manchester Metropolitan University, UK
Ioannis Papaefstathiou, Technical University of Crete, GR
Franz-Josef Pfreundt, Fraunhofer ITWM, DE
Bertil Schmidt, Nanyang Technological University, SG
Thomas Steinke, Zuse Institute, Berlin, DE
Robert Strzodka, Max Planck Center for Computer Science, DE
Carsten Trinitis, Technische Universität München, DE
Josef Weidendorfer, Technische Universität München, DE
Jan-Phillipp Weiss, KIT, DE
Gerhard Wellein, University Erlangen-Nuremberg, DE
Stephan Wong, Delft University of Technology, NL
Ren Wu, HP Labs, Palo Alto, US
Peter Zinterhof jun., University of Salzburg, AT
Yunquan Zhang, Chinese Academy of Sciences, Beijing, CN

Steering Committee

Lars Bengtsson, Chalmers University, SE
Ren Wu, HP Labs, Palo Alto, US

Workshop Organizers

Anders Hast, University in Gävle, SE
Josef Weidendorfer, Technische Universität München, DE
Jan-Phillipp Weiss, KIT, DE