The 6th Workshop on
UnConventional High Performance Computing 2013 (UCHPC 2013)
August 27, Aachen, Germany

held in conjunction with
Euro-Par 2013, August 26 - August 30, 2013
Aachen, Germany

News
Background
Topics
Best Paper
Program
Invited Talks
Submission
Important Dates
Committees
Organizers

Call for Papers
in txt format

Previous UCHPC
Workshops:
2012 @ EuroPar'12
2011 @ EuroPar'11
2010 @ EuroPar'10
2009 @ CF'09
2008 @ ICCSA'08


EuroPar 2013
Conference Home



Photo by ℵ (Aleph)

News

September 2, 2013: Talk slides added (if available), see program below

September 2, 2013: Best Paper Award Winner with pictures

August 26, 2013: Program change due to unavailability of 1st invited speaker: there will be a panel discussion instead (see below)

July 16, 2013: The program is now available, including two invited talks!

May 24, 2013: Submission deadline extended to June 10!

Feb 27, 2013: Submission is now open

Background

Recent issues with the power consumption of conventional HPC hardware results in both new interest in accelerator hardware and in usage of mass-market hardware originally not designed for HPC. The most prominent examples are GPUs, but FPGAs, DSPs and embedded designs are also possible candidates to provide higher power efficiency, as they are used in energy-restriced environments, such as smartphones or tablets. The so-called "dark silicon" forecast, i.e. not all transistors may be active at the same time, may lead to even more specialized hardware in future mass-market products. Exploiting this hardware for HPC can be a worthwhile challenge.

As the word "UnConventional" in the title suggests, the workshop focuses on usage of hardware or platforms for HPC, which are not (yet) conventially used today, and may not be designed for HPC in the first place. Reasons for its use can be raw computing power, good performance per watt, or low cost in general. To address this unconventional hardware, often, new programming approaches and paradigms are required to make best use of it. A second focus of the workshop is on innovative, (yet) unconventional new programming models.

To this end, UCHPC tries to capture solutions for HPC which are unconventional today but could become conventional and significant tomorrow, and thus provide a glimpse into the future of HPC.

Topics

The goal of the workshop is to present latest research in how hardware and software (yet) unconventional for HPC is or can be used to reach goals such as best performance per watt. UCHPC also covers according programming models, compiler techniques, and tools. Thus, suggested topics for papers include, but are not limited to the following:
  • Innovative use of hardware and software unconventional for HPC
  • HPC applications or visualizations in connection with HPC on GPUs (GPGPU), using GPUs embedded on processor dies (as found in AMD Fusion/APUs, NVidia Denver, Intel Ivy Bridge), Intel's MIC and SCC, low power/embedded processors (including DSPs, Adapteva Epiphany), FPGAs (e.g. Convey), Tilera's tile-based many-core processors, IBM Cell BE, accelerators, visualization cards, etc.
  • Cluster/Grid solutions using unconventional hardware, e.g. clusters of game consoles, nodes using GPUs, Low Power/Embedded Processors, MPSoCs, new many-cores from Intel and/or ARM designs, Mac Minis/AppleTVs, FPGAs etc.
  • Heterogeneous computing on hybrid platforms
  • Work on and use of new programming models and paradigms needed to support unconventional hardware, and hybrid/hierarchical combinations with more conventional systems. Examples are OpenACC, OpenCL, Cilk+, and task-based approaches for heterogeneous systems
  • Performance and scalability studies in HPC using unconventional hardware
  • Reconfigurable computing for HPC
  • Performance modeling, analysis and tools for HPC with unconventional hardware
  • New or adapted/extended (parallel) programming models for HPC with unconventional hardware


Best Paper Award

The first time for UCHPC, there will be a best paper award. For the winner, we have a special reward: a Samsung laptop with an AMD APU processor, sponsored by AMD.

The winner was the paper "PyDac: A Resilient Run-time Framework for Divide-and-Conquer Applications on a Heterogeneous Many-core Architecture" by Bin Huang, Ron Sass, Nathan Debardeleben and Sean Blanchard. Congratulations! Here are some pictures from the ceremony:


Program

The workshop takes place on Tuesday, August 27, 2013, in room SuperC-Generali.

Time  
9:00 Opening
Josef Weidendorfer, Jens Breitbart
  Session 1 (WE2)
Chair: Josef Weidendorfer
 
9:15 Panel Discussion
How to solve the power issue for future HPC systems?
Panelists: Satoshi Matsuoka (Tokyo Inst. of Techn.), Tim Mattson (Intel), Oliver Pell (Maxeler Technologies), Martin Schulz (LLNL), Carsten Trinitis (TUM and Univ. of Bedfordshire)
The panel replaces the invited talk "Mobile Processors for HPC: The Mont-Blanc Project" by Daniele Tafani (Leibniz Supercomputing Centre) due to unavailability
10:00 PyDac: A Resilient Run-time Framework for Divide-and-Conquer Applications on a Heterogeneous Many-core Architecture (slides)
Bin Huang, Ron Sass, Nathan Debardeleben and Sean Blanchard
10:30 Coffee Break
  Session 2 (WF2)
Chair: Jens Breitbart
 
11:00 Investigating the Integration of Supercomputers and Data-Warehouse Appliances (slides)
Ron A. Oldfield, George Davidson, Craig Ulmer and Andrew Wilson
11:30 Investigation of Parallel Programmability and Performance of a Calxeda ARM Server Using OpenCL (slides)
David Richie, James Ross, Jordan Ruloff, Song Park, Lori Pollock and Dale Shires
12:00 Active data structures on GPGPUs (slides)
John T. O'Donnell, Cordelia Hall, Stuart Monro
12:30 Lunch
  Session 3 (WG2)
Chair: Peter Zinterhof
14:30 Architecture of a High-speed MPI_Bcast Leveraging Software-Defined Network (slides)
Khureltulga Dashdavaa, Susumu Date, Hiroaki Yamanaka, Eiji Kawai, Yasuhiro Watashiba, Kohei Ichikawa, Hirotake Abe and Shinji Shimojo
15:00 Invited Talk 2
HPC Acceleration with Data Flow Programming (slides)
Oliver Pell, Maxeler Technologies
15:45 Best Paper Award Ceremony and Workshop Closing


Invited talks

Embedded Processors for HPC: The Mont-Blanc Project
Daniele Tafani, Leibniz Supercomputing Centre

    Energy efficiency is a primary concern for the design of any computer system and it is unanimously recognized that the development of future Exascale systems will be strongly constrained by their power consumption.

    The Mont-Blanc project has set itself the objective to design a new type of computer architecture capable of defining future global High Performance Computing (HPC) standards that will deliver Exascale performance while using 15 to 30 times less energy. The reduction of energy consumption will be achieved by developing a full energy-efficient HPC prototype using low-power, commercially available, embedded technology.

    The project is coordinated by the Barcelona Supercomputing Center (BSC) and has a budget of over 14 million Euros, including over 8 million Euros funded by the European Commission. The talk will cover the Mont-Blanc project strategy for addressing the energy consumption challenge of future Exascale system deployment from the hardware, software and infrastructure perspective.

HPC Acceleration with Data Flow Programming
Oliver Pell, Maxeler Technologies

    Data movement is the major challenge in current and future computing systems, both from the perspective of pure performance and energy efficiency. Many HPC applications are limited by memory bandwidth and demonstrate poor scaling on multi-core CPUs, and larger hierarchical cache structures only go some way towards helping this. At the same time, the energy cost to move data to and from memory already dwarfs the energy needed to perform arithmetic operations.

    Dataflow computing is an alternative computational paradigm which focuses on optimizing data movement and describes computation as an effect of this movement rather than the cause. Programs can be expressed as dataflow graphs, which can then be mapped directly into parallel pipelined implementations on Dataflow Engines (DFEs) based on reconfigurable logic. By running at relatively low clock frequencies (a few hundred MHz) and exploiting the implicit parallelism in the dataflow graph DFEs are very power efficient, while significantly improving the efficiency of memory access.

    Maxeler has developed a range of dataflow computing systems which have been shown to outperform conventional CPU systems by 10-50x in performance per unit space and power for a range of applications. This talk will cover the basics of dataflow computing, describe how programs can be described in this manner using MaxCompiler and discuss some results both from scientific research and commercial HPC applications.


Paper Submission, Registration, and Publication

Workshop papers must not exceed ten single-spaced, single-column pages (LNCS style). On acceptance of the submission, at least one author is required to register for workshop attendance at Euro-Par 2013 and present the paper in the workshop session.

Upload your submission to our submission server in PDF format. It must not be simultaneously submitted to the main conference or any other publication outlet.

For the workshop, we will prepare hand-outs with the revised papers. These will be published after the conference in the workshop proceedings of Euro-Par 2013, part of the LNCS series of Springer.


Important Dates

June 10, 2013: Submission deadline
July 8, 2013: Notification of acceptance
July 31, 2013: Camera ready, revised papers due
August 27/28, 2013: UCHPC'13 Workshop


Committees

International Program Committee

David A. Bader, Georgia Tech, US
Michael Bader, Technische Universität München, DE
Denis Barthou, Universite de Bordeaux, FR
Alex Bartzas, National Technical University of Athens, GR
Lars Bengtsson, Chalmers University of Technology, SE
Jens Breitbart, Heidelberg University, DE
Giorgos Dimitrakopoulos, Democritus University of Thrace, GR
Karl Fürlinger, LMU, DE
Dominik Goeddeke, TU Dortmund, DE
Georg Hager, FAU Erlangen-Nuremberg, DE
Frank Hannig, FAU Erlangen-Nuremberg, DE
Anders Hast, Uppsala University, SE
Rainer Keller, Hochschule für Technik, Stuttgart, DE
Gaurav Khanna, University of Massachusetts Dartmouth, US
Harald Köstler, FAU Erlangen-Nuremberg, DE
Manfred Mücke, Sustainable Computing Research, AT
Andy Nisbet, Manchester Metropolitan University, UK
Ioannis Papaefstathiou, Technical University of Crete, GR
Bertil Schmidt, University Mainz, DE
Ioannis Sourdis, Chalmers University of Technology, SE
Josef Weidendorfer, Technische Universität München, DE
Jan-Philipp Weiss, COMSOL, SE
Stephan Wong, Delft University of Technology, NL
Ren Wu, AMD, US
Yunquan Zhang, Chinese Academy of Sciences, Beijing, CN
Peter Zinterhof jun., University of Salzburg, AT

UCHPC Steering Committee

Lars Bengtsson, Chalmers University of Technology, SE
Anders Hast, Uppsala University, SE
Josef Weidendorfer, Technische Universität München, DE
Jan-Philipp Weiss, COMSOL, SE
Ren Wu, AMD, US


UCHPC'13 Workshop Organizers

Jens Breitbart, Heidelberg University, DE
Anders Hast, Uppsala University, SE
Josef Weidendorfer, Technische Universität München, DE